BLAS Level 3 Routines

BLAS Level 3 routines perform matrix-matrix operations. The following table lists the BLAS Level 3 routine groups and the data types associated with them.

Routine Group

Data Types

Description

gemm

half, float, double, std::complex<float>, std::complex<double>, mixed

Computes a matrix-matrix product with general matrices.

hemm

std::complex<float>, std::complex<double>

Computes a matrix-matrix product where one input matrix is Hermitian and one is general.

herk

std::complex<float>, std::complex<double>

Performs a Hermitian rank-k update.

her2k

std::complex<float>, std::complex<double>

Performs a Hermitian rank-2k update.

symm

float, double, std::complex<float>, std::complex<double>

Computes a matrix-matrix product where one input matrix is symmetric and one matrix is general.

syrk

float, double, std::complex<float>, std::complex<double>

Performs a symmetric rank-k update.

syr2k

float, double, std::complex<float>, std::complex<double>

Performs a symmetric rank-2k update.

trmm

float, double, std::complex<float>, std::complex<double>

Computes a matrix-matrix product where one input matrix is triangular and one input matrix is general.

trsm

float, double, std::complex<float>, std::complex<double>

Solves a triangular matrix equation (forward or backward solve).

  • The BLAS functions are blocked where possible to restructure the code in a way that increases the localization of data reference, enhances cache memory use, and reduces the dependency on the memory bus.

  • The code is distributed across the processors to maximize parallelism.

Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.